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5 ghz t o 11 g hz gaas, phemt, mmic, low noise amplifier data sheet hmc902lp3e rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is ass umed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or p atent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2018 analog devices, i nc. all rights reserved. technical support www.analog.com features low n oise f igure: 1.8 db typical high g ai n: 19.5 db high p1db o utput p ower: 16 dbm typical single s upply: 3.5 v at 80 ma output ip3: 28 dbm 50 ? matched i nput/ o utput self b iased with optional bias control for quiescent drain control ( i dq ) reduction. 3 mm 3 mm, 16 - lead lfcsp : 9 mm2 applications point to p oint r adios point to multi p oint r adios military and s pace test i nstrumentation functional block dia gram nic nic rf in gnd nic nic v dd 2 v dd 1 nic nic rf out gnd gnd nic v gg 1 v gg 2 nic hmc902lp3e package base 16 15 14 13 12 11 10 9 1 3 4 2 6 5 7 8 14524-001 figure 1 . general description the hmc902lp3e is a gallium arsenide ( gaas ), pseudomorphic high electron mobility transistor (phemt), monolithic microwave integrated circuit ( mmic ) l ow n oise a mplifier (lna), which is self biased with option al bias control f or idq reduction. the hmc 902lp3e is housed in a leadless 3 mm 3 mm plastic surface mount package. the amplifier operates between 5 ghz and 1 1 ghz , providing 19 .5 db of small signal gain, 1.8 db n oise figure, and 28 dbm of output ip3 , whi le requiring only 80 ma from a 3.5 v supply. the p1db output power of 16 dbm enables the lna to function as a local oscillator ( lo ) driver for balanced, i/q , or image rejec t mixers. the hmc902lp3e also features inputs/outputs that are dc blocked and internally matched to 50 ? , making it ideal for high capacity microwave radi os and c b and, very small aperture terminal ( vsat ) applications.
hmc902lp3e data sheet rev. e | page 2 of 13 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical specifications ............................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ..............................5 interface schematics .....................................................................5 typical performance characteristics ..............................................6 theory of operation .........................................................................9 applications information .............................................................. 10 evaluation printed circuit board (pcb) ................................ 11 application circuits ................................................................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 2 /2018 rev. d to re v. e changes to table 2 ............................................................................ 4 changes to ordering guide .......................................................... 13 10 /2017 rev. c to rev. d changes to tabl e 2 ............................................................................ 4 this hittite microwave products data sheet has been reformatted to meet the styles and standards of analog devices, inc. 7/ 2017 rev. 0 3. 0816 to rev. c updated format .................................................................. universal changed hmc902 to hmc902lp3e ......................... throughout changes to features section , applications section, general description section, and figure 1 ................................................... 1 changes to table 1 ............................................................................. 3 changes to figure 2 and table 3 ...................................................... 5 changes to typical performance characteristics section ........... 7 added theory of operation section and figure 21; renumbered sequentially ............................................................. 10 added applications information section ................................... 11 changes to table 4 .......................................................................... 12 added application circuit section , figure 23, and figure 24 ......... 13 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 14
data sheet hmc902lp3e rev. e | page 3 of 13 specifications electrical specifica tions t a = 25 c, v dd 1 = v dd 2 = 3.5 v, i dq = 80 ma . v gg 1 = v gg 2 = open for normal, self biased operation. table 1. p a ram eter symbol min typ max unit test conditions/comments frequenc y range 5 11 ghz gain 1 17 19.5 db gain variation over temperature 0.01 db/ c noise figure 1 nf 1.8 2. 2 db return loss input 12 db output 15 db output output power for 1 db compression 1 p1 d b 16 dbm saturated output power 1 p sat 17.5 dbm output third - order intercept ip3 28 dbm supply current i dq 80 110 ma v dd = 3.5 v, set v gg 2 = 0 v, v gg 1 = 0 v typical 1 board loss removed from gain, power , and noise figure measurement.
hmc902lp3e data sheet rev. e | page 4 of 13 absolute maximum rat ings table 2. parameter rating drain bias voltage 4.5 v radio frequency (rf) input power 1 0 db m gate bias voltage s v gg 1 ?2 v to +0.2 v v gg 2 ?2 v to +0.2 v channel temperature 150c continuous power dissipation, p diss (t = 85c, derate 7 mw/c above 85 c) 0.45 w thermal resistance (channel to ground pad ) 143.8 c/w storage temperature ? 65c to +150 c operating temperature ? 40c to +85 c electrosta tic discharge (esd) sensitivity human body model (hbm) class 1a, passed 250 v stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet hmc902lp3e rev. e | page 5 of 13 pin configuration and fu nction descriptions nic nic rf in gnd nic nic v dd 2 v dd 1 nic nic rf out gnd gnd nic v gg 1 v gg 2 nic hmc902lp3e top view (not to scale) package base 1 6 1 5 1 4 1 3 12 11 10 9 1 3 4 2 6 5 7 8 notes 1. nic = not internally connected. however, all data shown in this data sheet is measured with these pins connected to rf/dc ground externally. 2. exposed pad. the package bottom has an exposed metal ground paddle that must be connected to rf/dc ground. 14524-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1, 2, 5, 8, 11 to 13, 16 nic not internally connected. however, all data shown in this data sheet is measured with these pins connected to rf/dc ground externally. 3 rf in rf input. this pin is ac-coupled and matched to 50 . see figure 3 for the interface schematic. 4, 9 gnd ground. connect these pins to rf/dc ground. see figure 4 for the interface schematic. 6, 7 v gg 1, v gg 2 optional gate control for amplifier. if left open, the amplifier runs self biased at the standard current. applying a negative voltage reduces drain current. external capacitors are required (see figure 24). see figure 5 for the interface schematic. 10 rf out rf output. this pin is ac-coupled and matched to 50 . see figure 6 for the interface schematic. 14, 15 v dd 2, v dd 1 power supply voltage for the amplifier. see figure 23 and figure 24 for the application circuits. see figure 7 for the interface schematic. epad exposed pad. the package bottom has an exposed metal ground paddle that must be connected to rf/dc ground. interface schematics rf in 14524-003 figure 3. rf in interface schematic g nd 14524-004 figure 4. gnd interface schematic v gg 1, v gg 2 14524-005 figure 5. v gg 1 and v gg 2 interface schematic rf out 14524-006 figure 6. rf out interface schematic v dd 1, v dd 2 14524-007 figure 7. v dd 1 and v dd 2 interface schematic
hmc902lp3e data sheet rev. e | page 6 of 13 typical performance characteristics 25 ?25 ?15 ?5 5 15 3 5 7 9 11 13 response (db) frequency (ghz) s11 s21 s22 14524-008 fig ure 8 . broadband gain and return loss vs. frequency (board loss removed from gain, power , and noise figure measurem ents) 0 ?10 ?30 ?20 ?40 ?50 4 5 6 7 8 9 10 11 input return loss (db) frequency (ghz) +85c +25c ?40c 14524-009 figure 9 . input r eturn loss vs. frequency 6 5 4 3 2 1 0 noise figure (db) 4 5 6 7 8 9 10 11 frequency (ghz) +85c +25c ?40c 14524-010 figure 10 . noise fi gure vs. frequency at various temperature (boar d loss removed f rom gain, pow er, and noise figure measurements) 25 23 19 21 17 15 gain (db) 4 5 6 7 8 9 10 11 frequency (ghz) +85c +25c ?40c 14524-0 1 1 figure 11 . gain v s. frequency at various temperature (board loss removed from gain, power, and noise figure measurements) 0 ?10 ?30 ?20 ?40 ?50 4 5 6 7 8 9 10 11 output return loss (db) frequency (ghz) +85c +25c ?40c 14524-012 figure 12 . output return loss vs. frequency at various temperatures 35 30 20 25 15 10 output ip3 (dbm) 4 5 6 7 8 9 10 11 frequency (ghz) +85c +25c ?40c 14524-013 figure 13 . output ip3 vs. fr equency at various temperatures
data sheet hmc902lp3e rev. e | page 7 of 13 25 20 10 15 5 0 p1db (dbm) 4 5 6 7 8 9 10 11 frequency (ghz) +85c +25c ?40c 14524-014 figure 14 . output p 1db vs. frequency at various temperatures ( board loss removed f rom gain, pow er , and noise figure measurement s) 0 ?60 reverse isolation (db) ?50 ?40 ?30 ?20 ?10 4 5 6 7 8 9 10 11 frequency (ghz) +85c +25c ?40c 14524-015 figure 15 . reverse isolation vs. frequency at various temperature s 25 20 10 15 5 0 p sat (dbm) 4 5 6 7 8 9 10 11 frequency (ghz) +85c +25c ?40c 14524-016 figure 16 . p sat vs frequency at various . temperature s ( board loss removed from gain, power , and noise figure measurement s) 24 20 16 12 8 4 0 ?4 ?21 ?15 ?18 ?12 ?9 ?6 ?3 0 3 p out (dbm), gain (db), pae (%) input power (dbm) p out gain pae 14524-017 figure 17 . output power (p out ), gain, and power added efficiency (pae) vs. input power (board loss removed from gain, power, and noise figure measurements)
hmc902lp3e data sheet rev. e | page 8 of 13 22 8 3.0 3.5 4.0 gain (db), p1db (dbm) v dd (v) 10 12 14 16 18 20 7 0 noise figure (db) 1 2 3 4 5 6 gain p1db noise figure 14524-018 figure 18 . gain , p1db, and noise figure vs. supply voltage (v dd ) a t 7 ghz ( board loss removed f rom gain, pow er and noise figure measurement ) 88 78 ?30 ?24 ?21 ?15 ?9 ?6 ?3 ?12 ?27 ?18 0 3 i dd (ma) input power (dbm) 80 82 84 86 14524-019 figure 19 . supply curr ent (i dd ) vs. input power at 7 ghz 30 25 20 15 10 5 0 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 gain (db), ip3 (dbm) v gg 1, v gg 2 gate voltage (vdc) i dd (ma) 120 0 20 40 60 80 100 gain ip3 i dd 14524-020 figure 20 . gain, ip3 , a nd i dd vs. v gg 1, v gg 2 gate voltage at 7 ghz ( board l o s s removed from gain measurement , data taken at v dd 1 = v dd 2 = 3 v )
data sheet hmc902lp3e rev. e | page 9 of 13 theory of operation the hmc902lp3e is a gaas , mmic , phemt , lna . the hmc902lp3e a mplifier uses two gain stages in series. t he basic schematic for the amplifier is shown in figure 21 , which forms a lna opera ting from 5 ghz t o 11 ghz wi th excellent noise figure performance. v dd 1 v dd 2 v gg 1 v gg 2 rf in rf out 14524-021 figure 21 . basic schematic for hmc902lp3e the hmc902lp3e has single - ended input an d output ports w ith impedances that are nominally equal to 50 over the 5 ghz to 11 ghz f requency range. consequently, the device can be directly inser t ed into a 50 system with no required impedance matchi ng c ircuitry, which also means multiple hmc902lp3e am plifiers can be cascaded back to back without the need f or external matching circuitry. the input and output impedances are sufficiently stable vs. variations in temperature and supply voltage that no impedance matching compensation is required. it is critical to supply very low inductance ground connections to the package ground pad to en sure stable operation. to achieve optimal performance from the hmc902lp3e an d to prevent damage to the device, do not exceed the absolute maximum ratings.
hmc902lp3e data sheet rev. e | page 10 of 13 applications information the hmc902lp3e has v gg 1 and v gg 2 optional gate bias pins. when these pads are left open, the amplifier runs in sel f biased operation with typical i dq = 80 ma. figure 23 shows the basic connections for operating the hmc902lp3e in self biased operation mode. both rf in and rf out ports of hmc902lp3e have on - chip dc block capacitors , eliminating the need for external ac coupling capacitors. when using the optional v gg 1 and v gg 2 gate bias pins , use the recommended bias sequencing to prevent damage to the amplifier. the r ecommended b ias s equence during power - up is as follows: 1. connect to gnd . 2. set v gg 1 and v gg 2 to ? 2.0 v. 3. set v dd 1 and v dd 2 to 3.5 v . 4. increase v gg 1 and v gg 2 to a chieve typical i dq = 80 ma . 5. apply the rf signal . the recommended bias sequence during power - down is as follows: 1. tur n off the rf signal . 2. decre ase v gg 1 and v gg 2 to ? 2.0 v t o achieve typical i dq = 0 ma . 3. decrease v dd 1 and v dd 2 to 0 v . 4. increase v gg 1 and v gg 2 t o 0 v . the bias conditions previously listed (v dd = 3.5 v and i dq = 80 ma) are the recommended operating points to achieve optimum performance. the data used in this data sheet was taken with the recommended bias conditions. when u sing the hmc902lp3e with different bias conditions, different performance than what is shown in the typical performance characteristics section can result. decreasing the v dd level has negligible effect on gain and nf performance, but reduces the p1db , see figure 18 . for applications where the p1db requirement is not stringent, the hmc902lp3e can be down biased to red uce power consumption.
data sheet hmc902lp3e rev. e | page 11 of 13 evaluation printed circuit boar d (pcb ) the evaluation pcb of th e hmc902lp3e use s rf circuit design techniques. signal lines must have 50 ? impedan ce wh ereas the package ground leads and exposed paddle must be connected directly to the gro und plane similar to tha t shown in figure 22 . use a sufficient number of via holes to connect the top and bottom ground planes. the ev aluation board must be mounted to an appropriate heat sink. the evaluation pcb shown is available from analog devices, inc., upon request. 14524-022 f igure 22 . evaluation pcb (128395 - 1) table 4. bill of material s for the evaluation pcb it em description j1, j2 j3, j4, j6 to j8 c1, c4, c7, c10 c2, c5, c8, c11 c3, c6, c9, c12 u1 pcb s u b miniature version a (sma) connectors d c p in s 100 pf c ap acitor s , 0402 p a ckage 0.01 f c a p acitor s , 0402 p a ckage 4.7 f tantalum c a p acitors hmc902lp3e amplif i e r 128395-1 ev a luation p cb; circuit b oard m aterial: rogers 4350 or arlon 25fr
hmc902lp3e data sheet rev. e | page 12 of 13 application circuit s rf in v dd 2 v dd 1 rf out 16 15 14 13 12 1 1 10 9 1 3 4 2 6 5 7 8 c4 100pf c1 100pf + c9 4.7f c8 0.01f c7 100pf + c10 100pf c11 0.01f c12 4.7f 14524-023 figure 23 . standard (self biased) operation rf in v dd 2 v dd 1 rf out 16 15 14 13 12 1 1 10 9 1 3 4 2 6 5 7 8 + c9 4.7f c8 0.01f c7 100pf v gg 1 + c6 4.7f c5 0.01f c4 100pf + c10 100pf c11 0.01f c12 4.7f v gg 2 + c1 100pf c2 0.01f c3 4.7f 14524-024 figure 24 . gate control, reduced current operation
data sheet hmc902lp3e rev. e | page 13 of 13 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.95 1.70 sq 1.50 1 0.50 bsc bot t om view t o p view 16 5 8 9 12 13 4 exposed pad 0.45 0.40 0.35 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indic a t or 0.90 0.85 0.80 03-15-2017-b pkg-004863 compliant with jedec standards mo-220-veed-4. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. se a ting plane pin 1 indic a t or area options (see detail a) detail a (jedec 95) figure 25 . 16- lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.85 mm package height (hcp - 16- 1) dimensions shown in millimeters ordering guide model 1 temperature range lead finish package description package option hmc902lp3e ?40c to +85c 100% matte sn 16- lead lead frame chip scale package hcp -16-1 HMC902LP3ETR ?40c to +85c 100% matte sn 16- lead lead frame chip scale package hcp -16-1 129787- hmc902lp3e evaluation board 1 the hmc902lp3e and HMC902LP3ETR are rohs compliant parts. ? 2018 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14524 - 0- 2/18(e)

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